The SystemVerilog universal verification methodology (UVM) is an efficient way to generate tests and check results for functional verification, best used for block level IC or FPGA or other “smaller” ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...

The new memory library supports a wide spectrum of memory model variations including leading-edge protocols such as the high-bandwidth, low-pin-count HyperBus™ interface for HyperRAM™ and HyperFlash™ ...

This is not about replacing Verilog. It’s about evolving the hardware development stack so engineers can operate at the level of intent, not just implementation.

SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM), initially developed by Accellera and now standardized as IEEE 1800.2 ...

“To deliver the DDR3/DDR4 memory technologies in our advanced 64-bit AMD Opteron™ A-Series server SoC, formerly code-named 'Seattle,' we were an early user of the Synopsys DDR verification IP as part ...

While IC design complexity increases, the amount of time allotted for designing ICs remains about the same. That compels engineers to accelerate all the processes involved. I’m a member of a team that ...

Indeed, designers have embraced SystemVerilog—it's by far the fastest growing design/verification language in the world today (Fig. 1). "The ability to do assertions is significantly improved in ...

The productivity promise of portable stimulus has rapidly become well known in our industry. The high level of interest exhibited in the Accellera Portable Test and Stimulus Standard (PSS) makes sense ...