The AD9549, a dual-input network clock generator, claims to set a new standard for performance to maximize network uptime and increase system stability and reliability. Employing a unique architecture ...

RF instruments and wireless transceivers often feature an input for an external reference clock, such as the ubiquitous 10MHz reference input port found on RF instruments. Many of these same systems ...

It’s not always easy to design a ramp generator whose ramping frequency can be changed without manipulation of capacitors or inductors. Many ramp circuit designs are available, but they may not be ...

This paper discusses a novel idea on automatic clocks generation for a SoC. A standard configurable input file has all the required clock requirements in a SoC given by the designer. A scripting ...

In spread-spectrum and direct-sequence receivers, it’s often necessary to change the frequency of the clock oscillator, and thus the spreading-code clock, to lock the receiver’s reference pseudorandom ...

As chips grow ever larger and more complex, gate count and amount of embedded memory grow dramatically. The number of clock domains is also increasing steadily. Several dozen different clocks are ...

Phase-Locked Loops (PLLs) are commonly used to perform a variety of clock processing tasks, such as clock frequency multiplication and clock deskewing. PLLs, like many other analog IP macros, come ...

One of the most important steps in the design process is to identify how many different clocks to use and how to route them. This article tells you how to use routing resources efficiently.

DDR5 is the latest generation of PCDDR memory that is used in a wide range of application like data centers, Laptops and personal computers, autonomous driving systems, servers, cloud computing, and ...