EDN

Tool pinpoints false paths, steers designers away

SANTA CRUZ, Calif. — Startup FishTail Design Automation Inc. is targeting what sounds like a small niche, but the company says the potential benefits of its technology are huge. FishTail's tool, named ...
Semiconductor Engineering

Verification Of Multi-Cycle Paths And False Paths

All chip designers know that they must take special care to avoid metastability problems when they have multiple, asynchronous clock domains. In contrast, a design in which all clocks are synchronous ...
Semiconductor Engineering

Elimination Of Functional False Path During RDC Analysis

Reset domain crossing (RDC) issues can occur in sequential designs when the reset of a source register differs from the reset of a destination register, even if the data path is in the same clock ...
EDN

Reducing false errors in clock-domain crossing analysis

One of the biggest challenges of system-on-chip (SOC) designs is that different blocks operate on independent clocks. Integrating these blocks via the processor bus, memory ports, peripheral busses, ...
Electronic Design

Using Timing Constraints For Generating At-Speed Test Patterns

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...
Electronic Design

What are Analog Signal-Path Design Engineers Up To?

The current state of engineers working in analog signal-path engineering. Who they are, their ages, experience, and their time in the practice. Signal-path design refers to the process of designing ...